1. Field of the Invention
The present invention relates to a method for frequency control and orthogonal detection circuit and FSK (Frequency Shift Keying) receiver used for a digital radio receiver etc., particularly relates to a method for frequency control and orthogonal detection circuits and FSK receiver capable of reduction of a circuit size and improving precision of frequency control.
2. Description of the Related Art
Conventional orthogonal detection circuit is illustrated with reference to FIG. 4. The FIG. 4 is a block diagram of a conventional orthogonal detection circuit.
A conventional orthogonal detection circuit, as shown in FIG. 4, comprises a VCO (voltage control oscillator) 1 outputting an oscillating frequency, a phase shifter 2 shifting a phase of a signal 90xc2x0, the first mixing circuit 3a and the second mixing circuit 3b multiplying two signals, the first LPF (low path filter) 4a and the second LPF 4b removing a high frequency component, the first comparator 5a and the second comparator 5b outputting a digital signal over or not over a certain threshold value, the first moving average circuit 6a and the second moving average circuit 6b average an input signal, a phase angle detector 7 computing a phase angle, a differential analyzer 8 differentiating a phase angle signal, an integral electric discharge circuit 9 integrating an inputted signal for 1 symbol time, a phase detection circuit 10 detecting a changing point of a phase in an input signal, a synchronizing circuit 11 outputting a synchronized signal for an inputted signal showing detected changing point of a phase, a decision circuit 12 deciding the state of an integral signal, a standardizing circuit 13 outputting an appropriate integrated result based on the decision signal, a differential circuit 14 computing a difference between the output of the integral electric discharge circuit 9 and the output of the standardizing circuit 13, and an AFC (automatic frequency control) circuit 15 controlling local oscillation frequency of the VCO 1.
Herewith, functions of each part of a conventional orthogonal detection circuit will be specifically described with reference to the FIGS. 4 and 5. FIG. 5 is a drawing of a timing chart showing action of the conventional orthogonal detection circuit.
The VCO 1 is an oscillator working as a local oscillator of which oscillation frequency is controlled by the AFC circuit 15 that will be mentioned later.
The phase shifter 2 shifts the phase of a signal inputted from the VCO 1 90xc2x0.
The first mixing circuit 3a multiplies a received signal by a signal (oscillation frequency) inputted from the VCO 1 to output to the first LPF 4a. The signal outputted from the first mixing circuit 3a is one of the received signals and has the same phase component (hereafter, xe2x80x9cI phase componentxe2x80x9d) as that of the signal outputted by the VCO 1.
The second mixing circuit 3b multiplying a received signal to a shifted signal inputted from the phase shifter 2 to output to the second LPF 4b. A signal outputted by the second mixing circuit 3b is one of the received signal and a component orthogonal (hereafter, xe2x80x9cQ phase componentxe2x80x9d) to the signal outputted by the VCO 1.
The first LPF 4a removes a high frequency component of the signal of I phase component inputted from the first mixing circuit 3a to make, for example, a signal as shown in FIG. 5(a), and output to the first comparator 5a. 
The second LPF 4b removes a high frequency component of the signal of Q phase component inputted from the second mixing circuit 3b to make, for example, a signal as shown in FIG. 5(b), and output to the second comparator 5b. 
The first comparator 5a detects a signal inputted from the first LPF 4a over a certain threshold value; if the signal is over the threshold value, outputs 1 bit digital signal representing xe2x80x9c1xe2x80x9d, and if not over, outputs 1 bit digital signal representing xe2x80x9c0xe2x80x9d.
This means, for example, when a signal of the FIG. 5(a) is inputted to the first comparator 5a, the first comparator 5a outputs a signal as shown in the FIG. 5(c).
The second comparator 5b, as same as the first comparator 5a, detects a signal inputted from the second LPF 4b over a certain threshold value; if the signal is over the threshold value, outputs 1 bit digital signal representing xe2x80x9c1xe2x80x9d and if not over, outputs 1 bit digital signal representing xe2x80x9c0xe2x80x9d.
This means, for example, when a signal of the FIG. 5(b) is inputted to the second comparator 5b, the second comparator 5b outputs a signal as shown in the FIG. 5(d).
Hereafter, a signal outputted by the first comparator 5a is named xe2x80x9cquantized signal Ixe2x80x9d and a signal outputted by the second comparator 5b is named xe2x80x9cquantized signal Qxe2x80x9d.
The first moving average circuit 6a averages a quantized signal I inputted from the first comparator 5a to generate a signal with a gradually changed wave form. Specifically, for example, when a signal shown in the FIG. 5(c) is inputted, the first moving average circuit 6a outputs a signal with a wave form shown in the FIG. 5(e).
The second moving average circuit 6b averages a quantized signal Q inputted from the second comparator 5b to generate a signal with a gradually changed wave form. Specifically, for example, when a signal shown in the FIG. 5(d) is inputted, the second moving average circuit 6b outputs a signal with a wave form shown in the FIG. 5(f).
The phase angle detector 7 divides a signal inputted from the second moving average circuit 6b with a signal inputted from the first moving average circuit 6a, and compute arctangent of the quotient yielded by the division to output to the differential analyzer 8.
If a signal inputted from the first moving average circuit 6a is assumed xe2x80x9cIxe2x80x9d and a signal inputted from the second moving average circuit 6b is assumed xe2x80x9cQxe2x80x9d, a signal of the phase angle (a phase angle signal) xcex8 outputted by the phase angle detector 7 is expressed by the following formula (1).
xcex8=tanxe2x88x921(Q/I)xe2x80x83xe2x80x83[Formula 1]
In the phase angle detector 7, the phase angle signal computed based on the [Formula 1] has specifically the wave form shown in the FIG. 5(g).
The differential analyzer 8 differentiates the phase angle signal inputted from the phase angle detector 7 by time and outputs the change of the angle as a signal expressed by a digital signal of at least 2 bits as shown in the FIG. 5(h).
In other words, in the FIG. 5(h), a signal expressing xe2x80x9cxe2x88x921xe2x80x9d, a signal expressing xe2x80x9c+1xe2x80x9d, and a signal expressing xe2x80x9c0xe2x80x9d are outputted for start of gradual decrease in the strength of the phase angle signal, start of gradual increase in the strength of the phase angle signal, no change of the strength of the phase angle signal, respectively.
Hereafter, the signal outputted by the differential analyzer 8 is called xe2x80x9cEye-patternxe2x80x9d.
For reference, plus and minus of a signal are commonly expressed using MSB (most significant bit) used for digital signal. For example, xe2x80x9cxe2x88x921xe2x80x9d, xe2x80x9c+1xe2x80x9d, and xe2x80x9c0xe2x80x9d are expressed as xe2x80x9c11xe2x80x9d, xe2x80x9c01xe2x80x9d, and xe2x80x9c00xe2x80x9d, respectively.
The integral electric discharge circuit 9 computes the integral value of Eye-pattern inputted from the differential analyzer 8 for every 1 symbol time based on the synchronized signal inputted from synchronizing circuit 11, that will be mentioned later, at each 1 symbol time, to output as an integral signal. The integral signal is reset to xe2x80x9c0xe2x80x9d for each 1 symbol, as shown in the FIG. 5(i) to become a function increasing and decreasing with approximately constant proportions.
The phase detection circuit 10 detects a point (change point) (the point A to point E in the FIG. 5), in which the change of a phase become discrete, on the basis of quantized signal I and quantized signal Q inputted from the first comparator 5a and the second comparator 5b, respectively, and output a signal showing detection of the change point of the phase to the synchronizing circuit 11.
The point (change point), in which the change of a phase become discrete, is the point in which progress of a phase reverses; for example, as seen by comparing a phase change in ranges A-B with B-C before and after the point B of FIGS. 5(c) and (d).
This means that in A-B range, the quantized signal I of the FIG. 5(c) more progresses and in B-C, the quantized signal Q of the FIG. 5(d) more progresses.
More specifically, the phase detection circuit 10 monitors the quantized signal I and the quantized signal Q; when in spite of no change of one signal, the other signal has changed twice, counts time from the first change to the second change to detect an instance of change point of the phase in the point at a time half the counted time.
The synchronizing circuit 11 outputs a synchronized signal as the change point of a symbol to the integral electric discharge circuit 9, when receives an inputted signal expressing detection of change point of the phase from the phase detection circuit 10.
This means that a synchronized signal can be yielded as 1 symbol time passed for each detection of the point, in which the phase of either the signal inputted from the first comparator 5a or the second comparator 5b or both of them becomes discrete, by the functions of the phase detection circuit 10 and the synchronizing circuit 11.
The four-value decision circuit 12 makes a decision on the basis of a value, which the integral signal inputted from the integral electric discharge circuit 9 reached in a symbol interval.
Specifically, the four-value decision circuit 12 outputs a signal (decision signal) expressing any one of the following four kinds of state to standardizing circuit 13: an integral signal inputted from the integral electric discharge circuit 9 is minus resembling the interval of A-B of the point of the FIG. 5, and is under the threshold value Y; plus resembling the interval of B-C of the point of the FIG. 5, over the threshold value X; plus resembling the interval of C-D of the point of the FIG. 5, and not over the threshold value X; minus resembling the interval of D-E of the point of the FIG. 5, and not under the threshold value Y.
The standardizing circuit 13 receives an input of decision signal, and outputs the signal, resulted from appropriate integral electric discharge previously set and corresponding to respective four kinds of state that is expressed by the decision signal, to the differential circuit 14.
This means that the standardizing circuit 13 is set to output an ideal integral value to be outputted by the integral electric discharge circuit 9, when the frequency of a signal received corresponds to the frequency of a signal of the local oscillation. This ideal integral value is named xe2x80x9ctheoretical integral signalxe2x80x9d.
The differential circuit 14 computes difference between the result of integration outputted the integral electric discharge circuit 9 and the ideal integral value outputted by the standardizing circuit 13 to output to the AFC circuit 15.
The AFC circuit 15 controls to change the frequency of the local oscillation by the VCO 1 according to a difference inputted from the differential circuit 14.
This means that the AFC circuit 15 tunes the VCO 1 to meet the local oscillation frequency oscillated by the VCO 1 to the frequency of a signal received and shifted by fading.
Subsequently, the action of a conventional orthogonal detection circuit is described.
The frequency of a signal received is received with a little shift caused by effect of fading etc.
On the other hand, the VCO 1 oscillates in a frequency before the shift has occurred and the phase shifter 2 shifts the phase of a signal outputted by the VCO 1 90xc2x0.
The first mixing circuit 3a, the first LPF 4a, the first comparator 5a, and the first moving average circuit 6a multiplies s signal inputted from the VCO 1 by a signal received, removes a high frequency, generates a quantized signal I, and generates a signal with a wave form, as shown in the FIG. 5(e), gradually changing.
The second mixing circuit 3b, the second LPF 4b, the second comparator 5b, and the second moving average circuit 6b multiplies a signal outputted by the VCO 1 and shifted 90xc2x0 by the phase shifter 2, removes a high frequency, generates a quantized signal Q, and generates a signal with a wave form, as shown in the FIG. 5(f), gradually changing.
The phase angle detector 7 computes a phase angle made by respective signals inputted from the first moving average circuit 6a and the second moving average circuit 6b, and outputs to the differential analyzer 8 as a phase angle signal; and the differential analyzer 8 differentiates the phase angle signal by time and outputs a digital signal (Eye-pattern), that shows a direction of the signal of phase angle either in increase or in decrease, to the integral electric discharge circuit 9.
On the other hand, the functions of the phase detection circuit 10 and the synchronizing circuit 11 yields a synchronized signal for every 1 symbol time, the integral electric discharge circuit 9 integrates a eye-pattern that is inputted from the differential analyzer 8 and outputted to the four-value decision circuit 12 as an integrated value at every input of the synchronized signal.
The integrated value, as shown in the FIG. 5(i), expands radially from xe2x80x9c0xe2x80x9d corresponding to respective instances, for example, when the frequency of received signal corresponds to the frequency of the signal oscillated by the VCO 1.
Specifically, seemingly higher frequency received makes the integral value shift to a value increasing as shown in the point B to point C and point C-point D of the FIG. 5(i).
On the other hand, seemingly lower frequency received makes the integral value shift to a value decreasing as shown in the point A to point B and point D-point E of the FIG. 6(i).
And, the four-value decision circuit 12 outputs a decision signal to the standardizing circuit 13 according to the result of integration of the integral electric discharge circuit 9.
Besides, the standardizing circuit 13 outputs a value corresponding to the result of integration that is outputted by the integral electric discharge circuit 9, when the frequency of a received signal from the decision signal corresponds to the frequency of a signal oscillated by the VCO 1; the differential circuit 14 computes a difference between the value outputted by the standardizing circuit 13 and the result of integration actually outputted by the integral electric discharge circuit 9 to output to the AFC circuit 15.
Subsequently, the AFC circuit 15 controls the VCO 1 to make the difference between the result of the integration and the value (theoretical integral signal) outputted by the standardizing circuit 13 xe2x80x9c0xe2x80x9d, on the basis of the signal arrived from the differential circuit 14.
Through these steps, the frequency of the signal outputted by the VCO 1 is soon controlled to correspond to the signal being received.
For reference, the orthogonal detection circuit in FSK receiver mentioned before is exemplified by the description of Japanese Published Unexamined Patent Application No. 1997-116578, xe2x80x9cmany-valued FSKL demodulator circuitxe2x80x9d.
This many-valued FSKL demodulator circuit can reduce the occurrences of jitter and unclarity of decision output of degree of a rotation rate and improve preciseness of demodulation, even in a small difference between the modulation indices of the FSK modulation; and orthogonally detects an inputted signal in zero IF detection circuit, smoothes a component of same phase and orthogonal component, that was subjected to two-value-shaping by the comparator, in the moving average circuit, discharges integrally the difference between phase angles and their delayed phase angles corresponding to the same phase component and the orthogonal component, that have been smoothed in the integral discharge circuit, and decides the level of integrally discharged output in the decision circuit.
For reference, a table ROM is used for the many-valued FSKL demodulator circuit to know the phase angle xcex8 of the [Formula 1].
However, in the orthogonal detection circuit used in said conventional digital radio receiver, there is a problem that when a noise is mixed in a signal received, the AFC circuit cannot appropriately control a frequency, due to increased difference between the correct integral value outputted by the standardizing circuit and the incorrect integral value outputted by the integral discharge circuit, caused by a strong oscillation of the eye-pattern in the interval of the phase angle of which direction of rotation temporary reverses.
Besides, said conventional orthogonal detection circuit has generally a ROM (Read Only Memory) of the phase angle detection circuit computing [formula 1]. However, this case has a problem that a size of circuit cannot be satisfactory reduced even by using the ROM.
The present invention has a purpose to provide a method for frequency control and orthogonal detection circuit and FSK receiver capable of reduction of circuit size and appropriate control of frequency.
The present invention is a method for frequency control to integrate an axis-crossing signal showing that a signal point represented by phase I component being the same component and phase Q component being an orthogonal component, that have been made from a signal received and a signal outputted by the voltage control oscillator, crossed over any axis of I axis or Q axis being reference axes of IQ plane, for 1 symbol time, and detects the rotation of the signal point based on the result of integration, and controls the frequency of a signal outputted by the voltage control oscillator according to the rotation; detection of rotation, separately from the direction of rotation, allows reducing the circuit size temporary change of the direction of rotation of the signal point by a noise mixed in the signal received does not affect the rotation, and the frequency of the signal outputted by the voltage control oscillator can be appropriately controlled in a high preciseness.
The present invention is an orthogonal detection circuit, wherein concerning the signal point expressed by the I phase component and the Q phase component of a received signal and an oscillated signal, a detecting means for rotation direction detects the direction of rotation in the state of the signal point, the rotation rate detection means detects rotation rate by integrating an axis-crossing signal showing the crossing over the I axis or Q axis for a certain time, and the control means controls an oscillation frequency according to the rotation direction and rotation rate detected; and detection of rotation, separately from the direction of rotation, allows reducing the circuit size, temporary change of the direction of rotation of the signal point by a noise mixed in the signal received does not affect the rate of rotation, and the frequency of the signal outputted by the voltage control oscillator can be appropriately controlled in a high preciseness.
The present invention is an orthogonal detection circuit, wherein a decoder of rotation direction localizes the quadrant of the IQ plane having the signal point expressed by the I phase component and the Q phase component of a received signal and its delayed signal, and a frequency of an oscillated signal and outputs a difference between the value of the quadrant in the received signal and the value of the quadrant in the delayed signal, the synchronization means outputs a synchronized signal for every 1 symbol time, the first integral electric discharge circuit integrates and outputs the difference of values of quadrants that are inputted from the decoder of rotation direction for 1 symbol time according to the synchronized signal, a means for detection of crossing over the I axis detects that the signal, point crossed the I axis in the IQ plane and outputs a signal of detection of crossing over the I axis, a means for detection of crossing over the Q axis detects that the signal point crossed the Q axis in the IQ plane and outputs a signal of detection of crossing over the Q axis, the adder adds the signal of detection of crossing over the I axis and the signal of detection of crossing over the Q axis to output an axis crossing signal, the second integral electric discharge circuit integrates the axis crossing signal for 1 symbol time according to the synchronized signal to output a integral signal, the reversing circuit reverses the code of the integrated result in the second integral electric discharge circuit to output, the selector circuit selects and outputs the output of the second integral electric discharge circuit, when the input from the first integral electric discharge circuit is plus, and selects and outputs the output of the reversing circuit, when the input from the second integral electric discharge circuit is minus, and the frequency control means controls an oscillation frequency according to a signal inputted from the selector circuit; detection of rotation, separately from the direction of rotation, allows reducing the circuit size temporary change of the direction of rotation of the signal point by a noise mixed in the signal received does not affect the rotation, and the frequency of the signal outputted by the voltage control oscillator can be appropriately controlled in a high preciseness.
The present invention is a FSK receiver having said orthogonal detection circuit and capable of reduction of a circuit size and appropriate frequency control.